1 sy100s350 micrel, inc. m9999-042307 hbwhelp@micrel.com or (408) 955-1690 hex d-latch sy100s350 max. transparent propagation delay of 900ps min. master reset and enable pulse widths of 100ps i ee min. of ?8ma industry standard 100k ecl levels extended supply voltage option: v ee = ?.2v to ?.5v voltage and temperature compensation for improved noise immunity internal 75k ? input pull-down resistors more than 40% faster than fairchild approximately 30% lower power than fairchild function and pinout compatible with fairchild f100k available in 28-pin plcc package features description the sy100s350 offers six high-speed d-latches with both true and complement outputs, and is performance compatible for use with high-performance ecl systems. when both enable signals (e a and e b ) are at a logic low, the latches are transparent and the input signals( d 0 ? 5 ) appear at the outputs (q 0 ? 5 ) after a propagation delay. if either or both of the enable signals are at a logic high, then the latches store the last valid data present on its inputs before e a or e b went to a logic high. the master reset (mr) overrides all other input signals and takes the outputs to a logic low state. all inputs have 75k ? pull-down resistors. rev.: i amendment: /0 issue date: april 2007 block diagram d r d 5 q 5 e q 5 d r d 4 q 4 e q 4 d r d 3 q 3 e q 3 d r d 2 q 2 e q 2 d r d 1 q 1 e q 1 d r d 0 q 0 e q 0 e b mr e a pin function d 0 d 5 data inputs e a , e b common enable inputs (active low) mr asynchronous master reset input q 0 q 5 data outputs q 0 q 5 complementary data outputs v ees v ee substrate v cca v cco for ecl outputs pin names
2 sy100s350 micrel, inc. m9999-042307 hbwhelp@micrel.com or (408) 955-1690 package/ordering information ordering information package operating package lead part number type range marking finish sy100s350jc j28-1 commercial sy100s350jc sn-pb sy100s350jctr (1) j28-1 commercial sy100s350jc sn-pb sy100s350jz (2) j28-1 commercial sy100s350jz with matte-sn pb-free bar-line indicator sy100s350jztr (1, 2) j28-1 commercial sy100s350jz with matte-sn pb-free bar-line indicator notes: 1. tape and reel. 2. pb-free package is recommended for new designs. 28-pin plcc (j28-1) q 2 q 2 v cca v cc q 3 v cc d 2 v ee mr d 3 e a v ees 4 3 2 1 28 27 12 13 14 15 16 17 19 11 20 10 21 9 22 8 23 7 24 6 top view plcc j28-1 q 3 e b 26 18 25 5 d 1 d 0 q 0 v ees q 0 q 1 q 1 q 5 v ees d 5 q 5 d 4 q 4 q 4 each latch truth table (1) inputs outputs d n e a e b mr q n q n operating mode h l l l h l latch lllllh x x h l latched (2) latched (2) x h x l latched (2) latched (2) x x x h l h asynchronous notes: 1. h = high state l = low state x = don't care 2. retains data that is present before e positive transition.
3 sy100s350 micrel, inc. m9999-042307 hbwhelp@micrel.com or (408) 955-1690 dc electrical characteristics v ee = 4.2v to 5.5v unless otherwise specified; v cc = v cca = gnd symbol parameter min. typ. max. unit condition i ih input high current av in = v ih (max.) mr 250 dn 250 ea, eb 250 i ee power supply current 98 78 49 ma inputs open t a = 0 ct a = +25 ct a = +85 c symbol parameter min. max. min. max. min. max. unit condition t plh propagation delay 300 900 300 900 300 900 ps t phl d n to output t plh propagation delay 300 1000 300 1000 300 1000 ps t phl e a , e b to output t plh propagation delay 300 1200 300 1200 300 1200 ps t phl mr to output t tlh transition time 300 900 300 900 300 900 ps t thl 20% to 80%, 80% to 20% t s set-up time, d n to e n 500 500 500 ps t h hold time, d n to e n 500 500 500 ps t r release time, mr to e n 1000 1000 1000 ps t pw (l) pulse width, e a , e b 1000 1000 1000 ps t pw (h) pulse width, mr 1000 1000 1000 ps ac electrical characteristics v ee = 4.2v to 5.5v unless otherwise specified; v cc = v cca = gnd
4 sy100s350 micrel, inc. m9999-042307 hbwhelp@micrel.com or (408) 955-1690 timing diagrams enable timing note: v ee = 4.2v to 5.5v unless otherwise specified; v cc = v cca = gnd enable t phl , t plh t thl , t tlh 0.7 0.1 ns 0.95v 1.69v data output t w (l) 80% 50% 20% t phl , t plh t phl , t plh transparent latches 0.95v 1.69v transparent reset timing enable t phl , t plh data output t w (l) t phl , t plh t phl , t plh transparent latched transparent mr t r release time enable data t s t h data set-up and hold times notes: t s is the minimum time before the transition of the clock that information must be present at the data input. t h is the minimum time after the transition of the clock that information must remain unchanged at the data input.
5 sy100s350 micrel, inc. m9999-042307 hbwhelp@micrel.com or (408) 955-1690 28-pin plcc (j28-1) rev. a micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel + 1 (408) 944-0800 fax + 1 (408) 474-1000 web http://www.micrel.com the information furnished by micrel in this data sheet is believed to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intend ed for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant inj ury to the user. a purchaser s use or sale of micrel products for use in life support appliances, devices or systems is at purchaser s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2006 micrel, incorporated.
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